This invention relates to integrated circuit design, and particularly to compilers for developing a hardware description language of a circuit.
Integrated circuits (ICs) are often designed at a level of abstraction known as the registered transfer level (RTL), which is typically implemented in a hardware description language, such as Verilog HDL or VHDL. Verilog HDL is a hardware description language administered by the Institute of Electrical and Electronics Engineers (IEEE). At the RTL level of abstraction, the IC design is specified by functionally describing operations performed on data as they flow between circuit inputs, outputs and clocked registers. The Verilog HDL is both machine and human readable and is commonly used for development, verification, synthesis and testing of integrated circuit designs.
Most IC foundries require an RTL code describing the IC circuit to be fabricated. More particularly, the RTL code can be synthesized by the foundry to generate a gate-level description (netlist) for the IC. Synthesizing is performed using a technology library to map the RTL code into technology-dependent gate-level netlists, or mapped netlists. The RTL code is not technology dependent; the RTL code does not specify exact gates or logic devices to implement the design. The mapped netlist is technology dependent.
Many IC designers create IC designs using programming languages, such as C and C++. Code written in these languages is not easily synthesized or mapped to a given technology. Where an IC design is functionally described in C or C++, complex parsing is required to generate an RTL code, such as a Verilog HDL description of the circuit. Transformation from C/C++ to Verilog HDL is usually performed manually, meaning that process is highly labor-intensive. There is a need, therefore, for a compiler that transforms functional circuit models from languages such as C or C++, to an RTL description, such as Verilog HDL, so that the circuit design may be mapped, verified, modified, synthesized and tested.
In accordance with one aspect of the present invention, an integrated circuit functional description is transformed to an RTL description by modeling the integrated circuit as a generalized multiplexer. The multiplexer is defined by two groups of input variables X1, X2, . . . , Xs and Y1, Y2, . . . , Yn, and a group of outputs. Each input variable of the first group, X1, X2, . . . , Xs, is fixed as X1=a1, X2=a2, . . . , Xs=as, where a1, a2, . . . , as are fixed terms. No output depends on more than one variable of the second group. Output U[i] is defined, represented by F(a1,a2, . . . ,as,BIT(i,1),BIT(i,2),BIT(i,3), . . . ,BIT(i,n)), where i is a bit position of a number k. An output vector is constructed as UU1=U[0]⊕U[K], U[0]⊕U[K], . . . , U[0]⊕[K]. If an index j exists for which UU1=(BIT(0,j), BIT(1,j), . . . , BIT(Kxe2x88x921),j)), an RTL description of the integrated circuit is constructed as
F(a1,atxe2x88x921,0,Xt+1 . . . ,Xs,Y1,Y2, . . . ,Yn)(Xt) OR F(a1,atxe2x88x921,1,Xt+1 . . . ,Xs,Y1,Y2, . . . ,Yn) Xt.
Another aspect of the present invention is the provision of computer readable program that is embedded in a computer usable medium. The computer readable program includes program code that causes a computer to form an RTL description of an integrated circuit.